DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 244

MCU 5V 128K 100-TQFP

DF2345TE20

Manufacturer Part Number
DF2345TE20
Description
MCU 5V 128K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of DF2345TE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
71
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2345TE20
HD64F2345TE20

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Part Number
Manufacturer
Quantity
Price
Part Number:
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Manufacturer:
Renesas
Quantity:
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Part Number:
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Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 8 I/O Ports
8.3.2
Table 8.4 shows the port 2 register configuration.
Table 8.4
Name
Port 2 data direction register
Port 2 data register
Port 2 register
Note:
Port 2 Data Direction Register (P2DDR)
P2DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 2. P2DDR cannot be read; if it is, an undefined value will be read.
Setting a P2DDR bit to 1 makes the corresponding port 2 pin an output pin, while clearing the bit
to 0 makes the pin an input pin.
P2DDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its
prior state after a manual reset, and in software standby mode. As the TPU and 8-bit timer are
initialized by a manual reset, the pin states are determined by the P2DDR and P2DR
specifications.
Rev. 4.00 Feb 15, 2006 page 218 of 900
REJ09B0291-0400
Bit
Initial value
R/W
* Lower 16 bits of the address.
Register Configuration
Port 2 Registers
:
:
:
P27DDR
W
7
0
P26DDR
W
6
0
Abbreviation
P2DDR
P2DR
PORT2
P25DDR
W
5
0
P24DDR
W
4
0
R/W
W
R/W
R
P23DDR
W
3
0
Initial Value
H'00
H'00
Undefined
P22DDR
W
2
0
P21DDR
W
1
0
H'FEB1
Address *
H'FF61
H'FF51
P20DDR
W
0
0

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