DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 96

• Manufacturer Part Number: DF2345TE20
• Description: MCU 5V 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2345TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2345TE20; HD64F2345TE20

Section 3 MCU Operating Modes
Table 3.3
Name
Mode control register
System control register
System control register 2 *
Notes: 1. Lower 16 bits of the address.
3.2
3.2.1
MDCR is an 8-bit read-only register that indicates the current operating mode of the H8S/2345
Group.
Bit 7—Reserved: Read-only bit, always read as 1.
Bits 6 to 3—Reserved: Read-only bits, always read as 0.
Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the input levels at pins
MD
MDS2 to MDS0 are read-only bits-they cannot be written to. The mode pin (MD
levels are latched into these bits when MDCR is read. These latches are canceled by a power-on
reset, but are retained after a manual reset.
Rev. 4.00 Feb 15, 2006 page 70 of 900
REJ09B0291-0400
Bit
Initial value
R/W
Note: * Determined by pins MD
2
to MD
2. The SYSCR2 register can only be used in the F-ZTAT version. In the ZTAT, mask
Register Descriptions
Mode Control Register (MDCR)
ROM, and ROMless versions, this register cannot be written to and will return an
undefined value of read.
0
(the current operating mode). Bits MDS2 to MDS0 correspond to MD
MCU Registers
:
:
:
—
—
7
1
2
—
—
6
0
Abbreviation
MDCR
SYSCR
SYSCR2
2
to MD
—
—
5
0
0
.
—
—
4
0
R/W
R
R/W
R/W
—
—
3
0
Initial Value
Undetermined
H'01
H'00
MDS2
—*
R
2
MDS1
—*
R
1
2
to MD
2
Address *
H'FF3B
H'FF39
H'FF42
to MD
MDS0
0
) input
—*
R
0
0
.
1