DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 153
![MCU 5V 128K 100-TQFP](/photos/28/61/286108/100-tqfp_sml.jpg)
DF2345TE20
Manufacturer Part Number
DF2345TE20
Description
MCU 5V 128K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.DF2345TE20V.pdf
(929 pages)
Specifications of DF2345TE20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
71
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2345TE20
HD64F2345TE20
HD64F2345TE20
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2345TE20V
Manufacturer:
Renesas
Quantity:
222
Company:
Part Number:
DF2345TE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 153 of 929
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5.6.2
Figure 5.9 shows a block diagram of the DTC interrupt controller.
5.6.3
The interrupt controller has three main functions in DTC control.
(1) Selection of Interrupt Source
Interrupt sources can be specified as DTC activation requests or CPU interrupt requests by means
of the DTCE bit of DTCEA to DTCEE in the DTC.
After a DTC data transfer, the DTCE bit can be cleared to 0 and an interrupt request sent to the
CPU in accordance with the specification of the DISEL bit of MRB in the DTC.
When the DTC has performed the specified number of data transfers and the transfer counter value
is zero, the DTCE bit is cleared to 0 and an interrupt request is sent to the CPU after the DTC data
transfer.
On-chip
supporting
module
IRQ
interrupt
Block Diagram
Operation
Interrupt source
clear signal
Interrupt
request
Figure 5.9 Interrupt Control for DTC and DMAC
Interrupt controller
Selection
DTVECR
DTCER
circuit
Select
signal
clear signal
Clear signal
SWDTE
Determination of
Control logic
Rev. 4.00 Feb 15, 2006 page 127 of 900
priority
Section 5 Interrupt Controller
CPU interrupt
request vector
number
DTC activation
request vector
number
Clear signal
I, I2 to I0
REJ09B0291-0400
DTC
CPU
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