DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 134

MCU 5V 128K 100-TQFP

DF2345TE20

Manufacturer Part Number
DF2345TE20
Description
MCU 5V 128K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of DF2345TE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
71
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2345TE20
HD64F2345TE20

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2345TE20V
Manufacturer:
Renesas
Quantity:
222
Part Number:
DF2345TE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 5 Interrupt Controller
5.2.5
ISR is an 8-bit readable/writable register that indicates the status of IRQ7 to IRQ0 interrupt
requests.
ISR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 to 0—IRQ7 to IRQ0 flags (IRQ7F to IRQ0F): These bits indicate the status of IRQ7 to
IRQ0 interrupt requests.
Bit n
IRQnF
0
1
Rev. 4.00 Feb 15, 2006 page 108 of 900
REJ09B0291-0400
Bit
Initial value
R/W
Note: * Only 0 can be written, to clear the flag.
IRQ Status Register (ISR)
Description
[Clearing conditions]
[Setting conditions]
:
:
:
Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag
When interrupt exception handling is executed when low-level detection is set
(IRQnSCB = IRQnSCA = 0) and IRQn input is high
When IRQn interrupt exception handling is executed when falling, rising, or both-
edge detection is set (IRQnSCB = 1 or IRQnSCA = 1)
When the DTC is activated by an IRQn interrupt, and the DISEL bit in MRB of the
DTC is cleared to 0
When IRQn input goes low when low-level detection is set (IRQnSCB = IRQnSCA =
0)
When a falling edge occurs in IRQn input when falling edge detection is set
(IRQnSCB = 0, IRQnSCA = 1)
When a rising edge occurs in IRQn input when rising edge detection is set
(IRQnSCB = 1, IRQnSCA = 0)
When a falling or rising edge occurs in IRQn input when both-edge detection is set
(IRQnSCB = IRQnSCA = 1)
R/(W) *
IRQ7F
7
0
R/(W) *
IRQ6F
6
0
R/(W) *
IRQ5F
5
0
R/(W) *
IRQ4F
4
0
R/(W) *
IRQ3F
3
0
R/(W) *
IRQ2F
2
0
R/(W) *
IRQ1F
1
0
(Initial value)
R/(W) *
(n = 7 to 0)
IRQ0F
0
0

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