DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 164

• Manufacturer Part Number: DF2345TE20
• Description: MCU 5V 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2345TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2345TE20; HD64F2345TE20

Section 6 Bus Controller
Bit 7—Idle Cycle Insert 1 (ICIS1): Selects whether or not one idle cycle state is to be inserted
between bus cycles when successive external read cycles are performed in different areas.
Bit 7
ICIS1
0
1
Bit 6—Idle Cycle Insert 0 (ICIS0): Selects whether or not one idle cycle state is to be inserted
between bus cycles when successive external read and external write cycles are performed.
Bit 6
ICIS0
0
1
Bit 5—Burst ROM Enable (BRSTRM): Selects whether area 0 is used as a burst ROM
interface. In normal mode * , the selection can be made from the entire external space.
Burst ROM interface and PSRAM burst operation cannot be set at the same time.
Note: * ZTAT, mask ROM, and ROMless versions only.
Bit 5
BRSTRM
0
1
Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM
interface.
Bit 4
BRSTS1
0
1
Rev. 4.00 Feb 15, 2006 page 138 of 900
REJ09B0291-0400
Description
Idle cycle not inserted in case of successive external read cycles in different areas
Idle cycle inserted in case of successive external read cycles in different areas
Description
Idle cycle not inserted in case of successive external read and external write cycles
Idle cycle inserted in case of successive external read and external write cycles
Description
Area 0 is basic bus interface
Area 0 is burst ROM interface
Description
Burst cycle comprises 1 state
Burst cycle comprises 2 states
(Initial value)
(Initial value)
(Initial value)
(Initial value)