DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 292

• Manufacturer Part Number: DF2345TE20
• Description: MCU 5V 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2345TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2345TE20; HD64F2345TE20

Section 8 I/O Ports
8.11.2
Table 8.19 shows the port F register configuration.
Table 8.19 Port F Registers
Name
Port F data direction register
Port F data register
Port F register
Notes: 1. Lower 16 bits of the address.
Port F Data Direction Register (PFDDR)
PFDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port F. PFDDR cannot be read; if it is, an undefined value will be read.
PFDDR is initialized by a power-on reset, and in hardware standby mode, to H'80 in modes 1, 2,
4, 5, and 6 * , and to H'00 in modes 3 and 7 * . It retains its prior state after a manual reset, and in
software standby mode. The OPE bit in SBYCR is used to select whether the bus control output
pins retain their output state or become high-impedance when a transition is made to software
standby mode.
Rev. 4.00 Feb 15, 2006 page 266 of 900
REJ09B0291-0400
Bit
Modes 1, 2, 4, 5, 6 *
Initial value
R/W
Modes 3 and 7 *
Initial value
R/W
Modes 1, 2, 4, 5, and 6 *
Pin PF
input port when the bit is cleared to 0.
The input/output direction specified by PFDDR is ignored for pins PF
automatically designated as bus control outputs (AS, RD, HWR, and LWR).
2. Initial value depends on the mode.
Register Configuration
7
functions as the output pin when the corresponding PFDDR bit is set to 1, and as an
:
:
:
:
:
PF7DDR
W
W
7
1
0
PF6DDR
W
W
6
0
0
Abbreviation
PFDDR
PFDR
PORTF
PF5DDR
W
W
5
0
0
PF4DDR
W
W
4
0
0
R/W
W
R/W
R
PF3DDR
W
W
3
0
0
Initial Value
H'80/H'00 *
H'00
Undefined
PF2DDR
W
W
2
0
0
6
to PF
2
PF1DDR
3
, which are
W
W
1
0
0
Address *
H'FEBE
H'FF6E
H'FF5E
PF0DDR
W
W
0
0
0
1