DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 268

• Manufacturer Part Number: DF2345TE20
• Description: MCU 5V 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2345TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2345TE20; HD64F2345TE20

Section 8 I/O Ports
8.7.2
Table 8.11 shows the port B register configuration.
Table 8.11 Port B Registers
Name
Port B data direction register
Port B data register
Port B register
Port B MOS pull-up control register
Note:
Port B Data Direction Register (PBDDR)
PBDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port B. PBDDR cannot be read; if it is, an undefined value will be read.
PBDDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its
prior state after a manual reset, and in software standby mode. The OPE bit in SBYCR is used to
select whether the address output pins retain their output state or become high-impedance when a
transition is made to software standby mode.
Note: * Modes 1 to 3 are not available on the F-ZTAT version.
Rev. 4.00 Feb 15, 2006 page 242 of 900
REJ09B0291-0400
Bit
Initial value
R/W
Modes 1, 4, and 5 *
The corresponding port B pins are address outputs irrespective of the value of the PBDDR bits.
Modes 2 and 6 *
Setting a PBDDR bit to 1 makes the corresponding port B pin an address output, while
clearing the bit to 0 makes the pin an input port.
Modes 3 and 7 *
Setting a PBDDR bit to 1 makes the corresponding port B pin an output port, while clearing
the bit to 0 makes the pin an input port.
* Lower 16 bits of the address.
Register Configuration
Modes 2, 3, 6, and 7 are not available on the ROMless version.
:
:
:
PB7DDR
W
7
0
PB6DDR
W
6
0
PB5DDR
PBDDR
PBDR
PBPCR
Abbreviation
PORTB
W
5
0
PB4DDR
W
4
0
PB3DDR
R/W
W
R/W
R
R/W
W
3
0
Initial Value
H'00
H'00
Undefined
H'00
PB2DDR
W
2
0
PB1DDR
W
1
0
H'FEBA
Address *
H'FF6A
H'FF5A
H'FF71
PB0DDR
W
0
0