DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 140

• Manufacturer Part Number: DF2345TE20
• Description: MCU 5V 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2345TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2345TE20; HD64F2345TE20

Section 5 Interrupt Controller
5.4
5.4.1
Interrupt operations in the H8S/2345 Group differ depending on the interrupt control mode.
NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In
the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for
each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request. Interrupt
sources for which the enable bits are set to 1 are controlled by the interrupt controller.
Table 5.5 shows the interrupt control modes.
The interrupt controller performs interrupt control according to the interrupt control mode set by
the INTM1 and INTM0 bits in SYSCR, the priorities set in IPR, and the masking state indicated
by the I and UI bits in the CPU’s CCR, and bits I2 to I0 in EXR.
Table 5.5
Rev. 4.00 Feb 15, 2006 page 114 of 900
REJ09B0291-0400
Interrupt
Control Mode
0
—
2
—
Interrupt Operation
Interrupt Control Modes and Interrupt Operation
Interrupt Control Modes
INTM1 INTM0
0
1
SYSCR
0
1
0
1
Priority Setting
Registers
—
—
IPR
—
Interrupt
Mask Bits
I
—
I2 to I0
—
Description
Interrupt mask control is
performed by the I bit.
Setting prohibited
8-level interrupt mask control
is performed by bits I2 to I0.
8 priority levels can be set
with IPR.
Setting prohibited