DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 609

• Manufacturer Part Number: DF2345TE20
• Description: MCU 5V 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2345TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2345TE20; HD64F2345TE20

17.9.3
Flash memory erasing should be performed block by block following the procedure shown in the
erase/erase-verify flowchart (single-block erase) shown in figure 17.22.
The wait times (x, y, z, , ß,
and 2 (FLMCR1, FLMCR2) and the maximum number of programming operations (N) are shown
in table 20.10.
To perform data or program erasure, make a 1 bit setting for the flash memory area to be erased in
EBR1 or EBR2 at least (x) µs after setting the SWE bit to 1 in FLMCR1. Next, the watchdog timer
is set to prevent overerasing in the event of program runaway, etc. Set a value greater than (y + z +
carried out by setting the ESU bit in FLMCR2, and after the elapse of (y) µs or more, the operating
mode is switched to erase mode by setting the E bit in FLMCR1. The time during which the E bit
is set is the flash memory erase time. Ensure that the erase time does not exceed (z) ms.
Note: With flash memory erasing, preprogramming (setting all data in the memory to be erased
17.9.4
In erase-verify mode, data is read after memory has been erased to check whether it has been
correctly erased.
After the elapse of the erase time, erase mode is exited (the E bit in FLMCR1 is cleared to 0, then
the ESU bit in FLMCR2 is cleared to 0 at least ( ) µs later), the watchdog timer is cleared after the
elapse of ( ) µs or more, and the operating mode is switched to erase-verify mode by setting the
EV bit in FLMCR1. Before reading in erase-verify mode, a dummy write of H'FF data should be
made to the addresses to be read. The dummy write should be executed after the elapse of ( ) µs or
more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at
the latched address is read. Wait at least ( ) µs after the dummy write before performing this read
operation. If the read data has been erased (all 1), a dummy write is performed to the next address,
and erase-verify is performed. If the read data has not been erased, set erase mode again, and
repeat the erase/erase-verify sequence in the same way. However, ensure that the erase/erase-
verify sequence is not repeated more than (N) times. When verification is completed, exit erase-
verify mode, and wait for at least ( ) µs. If erasure has been completed on all the erase blocks,
clear the SWE bit in FLMCR1 to 0. If there are any unerased blocks, make a 1 bit setting in EBR1
or EBR2 for the flash memory area to be erased, and repeat the erase/erase-verify sequence in the
same way.
+ ß) µs as the WDT overflow period. After this, preparation for erase mode (erase setup) is
to 0) is not necessary before starting the erase procedure.
Erase Mode
Erase-Verify Mode
after bits are set or cleared in flash memory control registers 1
Rev. 4.00 Feb 15, 2006 page 583 of 900
REJ09B0291-0400
Section 17 ROM