DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 15

• Manufacturer Part Number: DF2345TE20
• Description: MCU 5V 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2345TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2345TE20; HD64F2345TE20

6.9
Section 7 Data Transfer Controller
7.1
7.2
7.3
7.4
7.5
Section 8 I/O Ports
8.1
8.2
6.8.3
6.8.4
Resets and the Bus Controller ........................................................................................... 169
Overview........................................................................................................................... 171
7.1.1
7.1.2
7.1.3
Register Descriptions ........................................................................................................ 174
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.2.9
Operation .......................................................................................................................... 182
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
7.3.9
7.3.10 Number of DTC Execution States........................................................................ 195
7.3.11 Procedures for Using DTC................................................................................... 197
7.3.12 Examples of Use of the DTC ............................................................................... 198
Interrupts ........................................................................................................................... 200
Usage Notes ...................................................................................................................... 200
Overview........................................................................................................................... 201
Port 1................................................................................................................................. 206
8.2.1
8.2.2
8.2.3
Bus Transfer Timing ............................................................................................ 169
External Bus Release Usage Note........................................................................ 169
Features................................................................................................................ 171
Block Diagram ..................................................................................................... 172
Register Configuration......................................................................................... 173
DTC Mode Register A (MRA) ............................................................................ 174
DTC Mode Register B (MRB)............................................................................. 176
DTC Source Address Register (SAR).................................................................. 177
DTC Destination Address Register (DAR).......................................................... 177
DTC Transfer Count Register A (CRA) .............................................................. 178
DTC Transfer Count Register B (CRB)............................................................... 178
DTC Enable Registers (DTCER) ......................................................................... 179
DTC Vector Register (DTVECR)........................................................................ 180
Module Stop Control Register (MSTPCR) .......................................................... 181
Overview.............................................................................................................. 182
Activation Sources ............................................................................................... 184
DTC Vector Table................................................................................................ 185
Location of Register Information in Address Space ............................................ 188
Normal Mode....................................................................................................... 189
Repeat Mode ........................................................................................................ 190
Block Transfer Mode ........................................................................................... 191
Chain Transfer ..................................................................................................... 193
Operation Timing................................................................................................. 194
Overview.............................................................................................................. 206
Register Configuration......................................................................................... 207
Pin Functions ....................................................................................................... 209
.............................................................................................................. 201
................................................................................. 171
Rev. 4.00 Feb 15, 2006 page xiii of xxiv