DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 43

• Manufacturer Part Number: DF2345TE20
• Description: MCU 5V 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2345TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2345TE20; HD64F2345TE20

Type
Interrupts
Address bus
Data bus
Bus control
Symbol
NMI
IRQ7 to
IRQ0
A
A
D
D
CS3 to
CS0
AS
RD
HWR
LWR
WAIT
23
0
15
0
to
to
FP-100B,
TFP-100B,
TFP-100G FP-100A
63
94, 93,
13, 12,
73 to 76
2, 1,
100, 99,
53 to 50,
48 to 41,
39 to 32
30 to 19,
17 to 14
94 to 97
70
71
72
73
74
Pin No.
65
96, 95,
15, 14,
75 to 78
4 to 1,
55 to 52,
50 to 43,
41 to 34
32 to 21,
19 to 16
96 to 99
72
73
74
75
76
I/O
Input
Output Address bus: These pins output an
I/O
Output Chip select: Signals for selecting
Output Address strobe: When this pin is low,
Output Read: When this pin is low, it
Output High write: A strobe signal that writes
Output Low write: A strobe signal that writes
Input
Input
Rev. 4.00 Feb 15, 2006 page 17 of 900
Name and Function
Nonmaskable interrupt: Requests a
nonmaskable interrupt. When this pin
is not used, it should be fixed high.
Interrupt request 7 to 0: These pins
request a maskable interrupt.
address.
Data bus: These pins constitute a
bidirectional data bus.
areas 3 to 0.
it indicates that address output on
the address bus is enabled.
indicates that the external address
space can be read.
to external space and indicates that
the upper half (D
bus is enabled.
to external space and indicates that
the lower half (D
bus is enabled.
Wait: Requests insertion of a wait
state in the bus cycle when
accessing external 3-state address
space.
7
15
Section 1 Overview
to D
to D
REJ09B0291-0400
0
) of the data
8
) of the data