DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 287

• Manufacturer Part Number: DF2345TE20
• Description: MCU 5V 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2345TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2345TE20; HD64F2345TE20

Port E Data Register (PEDR)
PEDR is an 8-bit readable/writable register that stores output data for the port E pins (PE
PEDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior
state after a manual reset, and in software standby mode.
Port E Register (PORTE)
PORTE is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port E pins (PE
If a port E read is performed while PEDDR bits are set to 1, the PEDR values are read. If a port E
read is performed while PEDDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTE contents are determined by the pin
states, as PEDDR and PEDR are initialized. PORTE retains its prior state after a manual reset, and
in software standby mode.
Port E MOS Pull-Up Control Register (PEPCR)
PEPCR is an 8-bit readable/writable register that controls the MOS input pull-up function
incorporated into port E on an individual bit basis.
Bit
Initial value
R/W
Note: * Determined by state of pins PE
Bit
Initial value
R/W
Bit
Initial value
R/W
:
:
:
:
:
:
:
:
:
PE7PCR
PE7DR
R/W
R/W
PE7
—*
7
0
R
7
7
0
PE6PCR
PE6DR
R/W
PE6
R/W
—*
R
6
0
6
6
0
7
to PE
PE5PCR
PE5DR
R/W
PE5
R/W
—*
0
R
5
0
5
5
0
) must always be performed on PEDR.
7
to PE
PE4PCR
PE4DR
0
R/W
R/W
PE4
.
—*
4
0
R
4
4
0
Rev. 4.00 Feb 15, 2006 page 261 of 900
PE3PCR
PE3DR
R/W
R/W
PE3
—*
3
0
R
3
3
0
PE2PCR
PE2DR
R/W
R/W
PE2
—*
2
0
R
2
2
0
PE1PCR
PE1DR
Section 8 I/O Ports
R/W
PE1
R/W
REJ09B0291-0400
—*
R
1
0
1
1
0
PE0PCR
PE0DR
7
R/W
R/W
PE0
to PE
—*
0
0
R
0
0
0
0
).