DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 14

• Manufacturer Part Number: DF2345TE20
• Description: MCU 5V 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2345TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2345TE20; HD64F2345TE20

Section 6 Bus Controller
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
Rev. 4.00 Feb 15, 2006 page xii of xxiv
Overview........................................................................................................................... 129
6.1.1
6.1.2
6.1.3
6.1.4
Register Descriptions ........................................................................................................ 132
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
Bus Control ....................................................................................................................... 140
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
Basic Bus Interface ........................................................................................................... 146
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
Burst ROM Interface......................................................................................................... 159
6.5.1
6.5.2
6.5.3
Idle Cycle .......................................................................................................................... 162
6.6.1
6.6.2
Bus Release....................................................................................................................... 165
6.7.1
6.7.2
6.7.3
6.7.4
6.7.5
Bus Arbitration.................................................................................................................. 168
6.8.1
6.8.2
Features................................................................................................................ 129
Block Diagram ..................................................................................................... 130
Pin Configuration................................................................................................. 131
Register Configuration......................................................................................... 131
Bus Width Control Register (ABWCR)............................................................... 132
Access State Control Register (ASTCR) ............................................................. 133
Wait Control Registers H and L (WCRH, WCRL).............................................. 134
Bus Control Register H (BCRH).......................................................................... 137
Bus Control Register L (BCRL) .......................................................................... 139
Area Divisions ..................................................................................................... 140
Bus Specifications................................................................................................ 142
Memory Interfaces ............................................................................................... 143
Advanced Mode................................................................................................... 143
Areas in Normal Mode (ZTAT, Mask ROM, and ROMless Versions Only) ...... 144
Chip Select Signals .............................................................................................. 145
Overview.............................................................................................................. 146
Data Size and Data Alignment............................................................................. 146
Valid Strobes........................................................................................................ 148
Basic Timing........................................................................................................ 149
Wait Control ........................................................................................................ 157
Overview.............................................................................................................. 159
Basic Timing........................................................................................................ 159
Wait Control ........................................................................................................ 161
Operation ............................................................................................................. 162
Pin States in Idle Cycle ........................................................................................ 165
Overview.............................................................................................................. 165
Operation ............................................................................................................. 165
Pin States in External Bus Released State............................................................ 166
Transition Timing ................................................................................................ 167
Usage Note........................................................................................................... 168
Overview.............................................................................................................. 168
Operation ............................................................................................................. 168
................................................................................................... 129