DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 589

• Manufacturer Part Number: DF2345TE20
• Description: MCU 5V 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2345TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2345TE20; HD64F2345TE20

17.6.5
The registers used to control the on-chip flash memory when enabled are shown in table 17.11.
In order for these registers to be accessed, the FLSHE bit must be set to 1 in SYSCR2.
Table 17.11 Flash Memory Registers
Notes: The registers listed in table 7.11 are enabled on the F-ZTAT version only. They do not exist
Register Name
Flash memory control register 1
Flash memory control register 2
Erase block register 1
Erase block register 2
System control register 2
RAM emulation register
on the ZTAT, mask ROM, and ROMless versions, so an undefined value will be returned if
they are read, and it is not possible to write to these registers.
1. Lower 16 bits of the address.
2. Flash memory registers share addresses with other registers. Register selection is
3. In modes in which the on-chip flash memory is disabled (modes 4 and 5), a read will
4. When a high level is input to the FWE pin, the initial value is H'80.
5. When a low level is input to the FWE pin, or if a high level is input and the SWE bit in
6. FLMCR1, FLMCR2, EBR1, and EBR2 are 8-bit registers. Only byte accesses are valid
Register Configuration
performed by the FLSHE bit in the system control register 2 (SYSCR2).
return H'00, and writes are invalid. Writes are also disabled when the FWE bit is cleared
to 0 in FLMCR1.
FLMCR1 is not set, these registers are initialized to H'00.
for these registers, the access requiring 2 states.
Abbreviation R/W
FLMCR1 *
FLMCR2 *
EBR1 *
EBR2 *
SYSCR2
RAMER
6
6
6
6
R/W *
R/W *
R/W *
R/W *
R/W
R/W
Rev. 4.00 Feb 15, 2006 page 563 of 900
3
3
3
3
Initial Value
H'00 *
H'00 *
H'00 *
H'00 *
H'00
H'00
4
5
5
5
REJ09B0291-0400
Section 17 ROM
Address *
H'FFC8 *
H'FFC9 *
H'FFCA *
H'FFCB *
H'FF42
H'FEDB
2
2
2
2
1