DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 269

MCU 5V 128K 100-TQFP

DF2345TE20

Manufacturer Part Number
DF2345TE20
Description
MCU 5V 128K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of DF2345TE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
71
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2345TE20
HD64F2345TE20

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2345TE20V
Manufacturer:
Renesas
Quantity:
222
Part Number:
DF2345TE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Port B Data Register (PBDR)
PBDR is an 8-bit readable/writable register that stores output data for the port B pins (PB
PBDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior
state after a manual reset, and in software standby mode.
Port B Register (PORTB)
PORTB is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port B pins (PB
If a port B read is performed while PBDDR bits are set to 1, the PBDR values are read. If a port B
read is performed while PBDDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTB contents are determined by the pin
states, as PBDDR and PBDR are initialized. PORTB retains its prior state after a manual reset, and
in software standby mode.
Bit
Initial value
R/W
Note: * Determined by state of pins PB
Bit
Initial value
R/W
:
:
:
:
:
:
PB7DR
R/W
PB7
—*
7
0
R
7
PB6DR
R/W
PB6
—*
6
0
R
6
7
to PB
PB5DR
R/W
PB5
—*
5
0
R
7
0
5
) must always be performed on PBDR.
to PB
PB4DR
0
.
R/W
PB4
—*
4
0
R
4
Rev. 4.00 Feb 15, 2006 page 243 of 900
PB3DR
R/W
PB3
—*
3
0
R
3
PB2DR
R/W
PB2
—*
2
0
R
2
PB1DR
Section 8 I/O Ports
R/W
REJ09B0291-0400
PB1
—*
1
0
R
1
PB0DR
7
R/W
PB0
to PB
—*
0
0
R
0
0
).

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