DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 844

• Manufacturer Part Number: DF2345TE20
• Description: MCU 5V 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2345TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2345TE20; HD64F2345TE20

Appendix B Internal I/O Register
SSR0—Serial Status Register 0
Rev. 4.00 Feb 15, 2006 page 818 of 900
REJ09B0291-0400
Bit
Initial value
Read/Write
Note: * Can only be written with 0 for flag clearing.
:
:
:
R/(W)*
Transmit Data Register Empty
TDRE
0
1
7
1
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and writes data to TDR
[Setting conditions]
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data can be written to TDR
Receive Data Register Full
R/(W)*
RDRF
0
1
6
0
[Clearing conditions]
• When 0 is written to RDRF after reading RDRF = 1
• When the DTC is activated by an RXI interrupt and reads data from RDR
[Setting condition]
When serial reception ends normally and receive data is transferred from RSR to RDR
Overrun Error
R/(W)*
ORER
0
1
5
0
[Clearing condition]
When 0 is written to ORER after reading ORER = 1
[Setting condition]
When the next serial reception is completed while RDRF = 1
Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its prior state.
Error Signal Status
R/(W)*
0
1
ERS
4
0
[Clearing conditions]
• On reset, or in standby mode or module stop mode
• When 0 is written to ERS after reading ERS = 1
[Setting condition]
When the error signal is sampled at the low level
Parity Error
R/(W)*
0
1
PER
3
0
[Clearing condition]
When 0 is written to PER after reading PER = 1
[Setting condition]
When, in reception, the number of 1 bits in the receive data plus the parity bit
does not match the parity setting (even or odd) specified by the O/E bit in SMR
Note: etu: Elementary Time Unit (the time taken to transmit one bit)
Transmit End
0
1
TEND
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and writes data to TDR
[Setting conditions]
• On reset, or in standby mode or module stop mode
• When the TE bit in SCR is 0 and the ERS bit is 0
• When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu
• When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu
R
after a 1-byte serial character is transmitted when GM = 0
after a 1-byte serial character is transmitted when GM = 1
2
1
Multiprocessor Bit
0
1
MPB
[Clearing condition]
When data with a 0 multiprocessor bit is received
[Setting condition]
When data with a 1 multiprocessor bit is received
H'FF7C
R
1
0
Multiprocessor Bit Transfer
0
1
MPBT
R/W
Data with a 0 multiprocessor bit is transmitted
Data with a 1 multiprocessor bit is transmitted
0
0
Smart Card Interface 0