DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 19

• Manufacturer Part Number: DF2345TE20
• Description: MCU 5V 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2345TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2345TE20; HD64F2345TE20

11.3 Operation .......................................................................................................................... 404
11.4 Interrupts ........................................................................................................................... 408
11.5 Usage Notes ...................................................................................................................... 408
Section 12 Serial Communication Interface (SCI)
12.1 Overview........................................................................................................................... 411
12.2 Register Descriptions ........................................................................................................ 416
12.3 Operation .......................................................................................................................... 440
12.4 SCI Interrupts.................................................................................................................... 470
12.5 Usage Notes ...................................................................................................................... 471
Section 13 Smart Card Interface
13.1 Overview........................................................................................................................... 477
11.2.4 Notes on Register Access..................................................................................... 402
11.3.1 Watchdog Timer Operation ................................................................................. 404
11.3.2 Interval Timer Operation ..................................................................................... 405
11.3.3 Timing of Setting Overflow Flag (OVF) ............................................................. 406
11.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF) ......................... 407
11.5.1 Contention between Timer Counter (TCNT) Write and Increment ..................... 408
11.5.2 Changing Value of CKS2 to CKS0...................................................................... 409
11.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 409
11.5.4 System Reset by WDTOVF Signal...................................................................... 409
11.5.5 Internal Reset in Watchdog Timer Mode............................................................. 410
12.1.1 Features................................................................................................................ 411
12.1.2 Block Diagram ..................................................................................................... 413
12.1.3 Pin Configuration................................................................................................. 414
12.1.4 Register Configuration......................................................................................... 415
12.2.1 Receive Shift Register (RSR) .............................................................................. 416
12.2.2 Receive Data Register (RDR) .............................................................................. 416
12.2.3 Transmit Shift Register (TSR) ............................................................................. 417
12.2.4 Transmit Data Register (TDR)............................................................................. 417
12.2.5 Serial Mode Register (SMR)................................................................................ 418
12.2.6 Serial Control Register (SCR).............................................................................. 421
12.2.7 Serial Status Register (SSR) ................................................................................ 425
12.2.8 Bit Rate Register (BRR) ...................................................................................... 429
12.2.9 Smart Card Mode Register (SCMR) .................................................................... 438
12.2.10 Module Stop Control Register (MSTPCR) .......................................................... 439
12.3.1 Overview.............................................................................................................. 440
12.3.2 Operation in Asynchronous Mode ....................................................................... 442
12.3.3 Multiprocessor Communication Function............................................................ 453
12.3.4 Operation in Clocked Synchronous Mode ........................................................... 461
..................................................................................... 477
Rev. 4.00 Feb 15, 2006 page xvii of xxiv
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