DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 48

MCU 5V 128K 100-TQFP

DF2345TE20

Manufacturer Part Number
DF2345TE20
Description
MCU 5V 128K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of DF2345TE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
71
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2345TE20
HD64F2345TE20

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2345TE20V
Manufacturer:
Renesas
Quantity:
222
Part Number:
DF2345TE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 2 CPU
2.1.2
The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.
There are also differences in the address space, CCR and EXR register functions, power-down
state, etc., depending on the product.
Rev. 4.00 Feb 15, 2006 page 22 of 900
REJ09B0291-0400
High-speed operation
Two CPU operating modes
Power-down state
Register configuration
The MAC register is supported only by the H8S/2600 CPU.
Basic instructions
The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the
H8S/2600 CPU.
Number of execution states
The number of execution states of the MULXU and MULXS instructions.
Instruction
MULXU
MULXS
All frequently-used instructions execute in one or two states
Maximum clock rate
8/16/32-bit register-register add/subtract : 50 ns
8
16 ÷ 8-bit register-register divide
16
32 ÷ 16-bit register-register divide
Normal mode (Supported on ZTAT, mask ROM, and ROMless versions only)
Advanced mode
Transition to power-down state by SLEEP instruction
CPU clock speed selection
Differences between H8S/2600 CPU and H8S/2000 CPU
8-bit register-register multiply
16-bit register-register multiply
Mnemonic
MULXU.B Rs, Rd
MULXU.W Rs, ERd
MULXS.B Rs, Rd
MULXS.W Rs, ERd
: 20 MHz
: 600 ns
: 600 ns
: 1000 ns
: 1000 ns
H8S/2600
3
4
4
5
Internal Operation
H8S/2000
12
20
13
21

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