DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 792

• Manufacturer Part Number: DF2345TE20
• Description: MCU 5V 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2345TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2345TE20; HD64F2345TE20

Appendix B Internal I/O Register
TIOR3L—Timer I/O Control Register 3L
Rev. 4.00 Feb 15, 2006 page 766 of 900
REJ09B0291-0400
Bit
Initial value
Read/Write
Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the
register operates as a buffer register.
:
:
:
Notes:
TGR3D I/O Control
0
1
IOD3
R/W
7
0
0
1
0
1
When the BFB bit in TMDR3 is set to 1 and TGR3D is used as a buffer register,
this setting is invalid and input capture/output compare is not generated.
1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and /1 is used as
the TCNT4 count clock, this setting is invalid and input capture is not generated.
0
1
0
1
0
1
*
IOD2
R/W
6
0
0
1
0
1
0
1
0
1
0
1
*
*
TGR3D
is output
compare
register
TGR3D
is input
capture
register
IOD1
R/W
5
0
Output disabled
Initial output is 0
output
Output disabled
Initial output is 1
output
Capture input
source is
TIOCD3 pin
Capture input
source is channel
4/count clock
Note: When the BFA bit in TMDR3 is set to 1 and TGR3C is used as a buffer register,
TRG3C I/O Control
IOD0
R/W
0
1
4
0
this setting is invalid and input capture/output compare is not generated.
0
1
0
1
IOC3
R/W
0
1
0
1
0
1
*
3
0
1 output at compare match
Toggle output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
0 output at compare match
0 output at compare match
Input capture at TCNT4 count-up/
count-down *
0
1
0
1
0
1
0
1
0
1
*
*
TGR3C
is output
compare
register
TGR3C
is input
capture
register
IOC2
R/W
2
0
H'FE83
1
Output disabled
Initial output is
0 output
Output disabled
Initial output is 1
output
Capture input
source is
TIOCC3 pin
Capture input
source is channel
4/count clock
IOC1
R/W
1
0
*: Don’t care
IOC0
R/W
0
0
1 output at compare match
Toggle output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
0 output at compare match
0 output at compare match
Input capture at TCNT4 count-up/
count-down
*: Don’t care
TPU3