DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 18

• Manufacturer Part Number: DF2345TE20
• Description: MCU 5V 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2345TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2345TE20; HD64F2345TE20

Section 10 8-Bit Timers
10.1 Overview........................................................................................................................... 371
10.2 Register Descriptions ........................................................................................................ 374
10.3 Operation .......................................................................................................................... 382
10.4 Interrupts ........................................................................................................................... 387
10.5 Sample Application........................................................................................................... 388
10.6 Usage Notes ...................................................................................................................... 389
Section 11 Watchdog Timer
11.1 Overview........................................................................................................................... 395
11.2 Register Descriptions ........................................................................................................ 398
Rev. 4.00 Feb 15, 2006 page xvi of xxiv
10.1.1 Features................................................................................................................ 371
10.1.2 Block Diagram ..................................................................................................... 372
10.1.3 Pin Configuration................................................................................................. 373
10.1.4 Register Configuration......................................................................................... 373
10.2.1 Timer Counters 0 and 1 (TCNT0, TCNT1) ......................................................... 374
10.2.2 Time Constant Registers A0 and A1 (TCORA0, TCORA1) ............................... 374
10.2.3 Time Constant Registers B0 and B1 (TCORB0, TCORB1) ................................ 375
10.2.4 Time Control Registers 0 and 1 (TCR0, TCR1) .................................................. 375
10.2.5 Timer Control/Status Registers 0 and 1 (TCSR0, TCSR1).................................. 378
10.2.6 Module Stop Control Register (MSTPCR) .......................................................... 381
10.3.1 TCNT Incrementation Timing ............................................................................. 382
10.3.2 Compare Match Timing....................................................................................... 383
10.3.3 Timing of External RESET on TCNT ................................................................. 385
10.3.4 Timing of Overflow Flag (OVF) Setting ............................................................. 385
10.3.5 Operation with Cascaded Connection.................................................................. 386
10.4.1 Interrupt Sources and DTC Activation ................................................................ 387
10.4.2 A/D Converter Activation.................................................................................... 387
10.6.1 Contention between TCNT Write and Clear........................................................ 389
10.6.2 Contention between TCNT Write and Increment ................................................ 390
10.6.3 Contention between TCOR Write and Compare Match ...................................... 391
10.6.4 Contention between Compare Matches A and B ................................................. 392
10.6.5 Switching of Internal Clocks and TCNT Operation............................................. 392
10.6.6 Usage Note........................................................................................................... 394
11.1.1 Features................................................................................................................ 395
11.1.2 Block Diagram ..................................................................................................... 396
11.1.3 Pin Configuration................................................................................................. 397
11.1.4 Register Configuration......................................................................................... 397
11.2.1 Timer Counter (TCNT)........................................................................................ 398
11.2.2 Timer Control/Status Register (TCSR) ................................................................ 399
11.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 401
..................................................................................................... 371
............................................................................................. 395