DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 412

• Manufacturer Part Number: DF2345TE20
• Description: MCU 5V 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2345TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2345TE20; HD64F2345TE20

Section 10 8-Bit Timers
10.3.5
If bits CKS2 to CKS0 in either TCR0 or TCR1 are set to B'100, the 8-bit timers of the two
channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit timer
mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1
(compare match counter mode). In this case, the timer operates as below.
16-Bit Counter Mode: When bits CKS2 to CKS0 in TCR0 are set to B'100, the timer functions
as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the
lower 8 bits.
Compare Match Counter Mode: When bits CKS2 to CKS0 in TCR1 are B'100, TCNT1 counts
compare match A’s for channel 0.
Channels 0 and 1 are controlled independently. Conditions such as setting of the CMF flag,
generation of interrupts, output from the TMO pin, and counter clear are in accordance with the
settings for each channel.
Note on Usage: If the 16-bit counter mode and compare match counter mode are set
simultaneously, the input clock pulses for TCNT0 and TCNT1 are not generated and thus the
counters will stop operating. Software should therefore avoid using both these modes.
Rev. 4.00 Feb 15, 2006 page 386 of 900
REJ09B0291-0400
Setting of compare match flags
Counter clear specification
Pin output
The CMF flag in TCSR0 is set to 1 when a 16-bit compare match event occurs.
The CMF flag in TCSR1 is set to 1 when a lower 8-bit compare match event occurs.
If the CCLR1 and CCLR0 bits in TCR0 have been set for counter clear at compare match,
the 16-bit counter (TCNT0 and TCNT1 together) is cleared when a 16-bit compare match
event occurs. The 16-bit counter (TCNT0 and TCNT1 together) is cleared even if counter
clear by the TMRI0 pin has also been set.
The settings of the CCLR1 and CCLR0 bits in TCR1 are ignored. The lower 8 bits cannot
be cleared independently.
Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR0 is in accordance with
the 16-bit compare match conditions.
Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR1 is in accordance with
the lower 8-bit compare match conditions.
Operation with Cascaded Connection