DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 143

MCU 5V 128K 100-TQFP

DF2345TE20

Manufacturer Part Number
DF2345TE20
Description
MCU 5V 128K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of DF2345TE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
71
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2345TE20
HD64F2345TE20

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2345TE20V
Manufacturer:
Renesas
Quantity:
222
Part Number:
DF2345TE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Table 5.8
Legend:
X : No operation. (All interrupts enabled)
IM : Used as interrupt mask bit
PR : Sets priority.
— : Not used.
Note:
5.4.2
Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by
means of the I bit in the CPU’s CCR. Interrupts are enabled when the I bit is cleared to 0, and
disabled when set to 1.
Figure 5.5 shows a flowchart of the interrupt acceptance operation in this case.
[1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
[2] The I bit is then referenced. If the I bit is cleared to 0, the interrupt request is accepted. If the I
[3] Interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to
[4] When an interrupt request is accepted, interrupt exception handling starts after execution of the
[5] The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on
[6] Next, the I bit in CCR is set to 1. This masks all interrupts except NMI.
Interrupt
Control
Mode
interrupt request is sent to the interrupt controller.
bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending.
the priority system is accepted, and other interrupt requests are held pending.
current instruction has been completed.
the stack shows the address of the first instruction to be executed after returning from the
interrupt handling routine.
: Interrupt operation control performed
0
2
1. Set to 1 when interrupt is accepted.
2. Keep the initial setting.
Interrupt Control Mode 0
INTM1
Operations and Control Signal Functions in Each Interrupt Control Mode
0
1
Setting
INTM0
0
0
Interrupt Acceptance
X
Control
— *
IM
I
1
X
8-Level Control
Rev. 4.00 Feb 15, 2006 page 117 of 900
I2 to I0
IM
— *
IPR
PR
Section 5 Interrupt Controller
2
Determination
Priority
Default
REJ09B0291-0400
T (Trace)
T

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