DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 22

• Manufacturer Part Number: DF2345TE20
• Description: MCU 5V 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2345TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2345TE20; HD64F2345TE20

17.7 Register Descriptions ........................................................................................................ 564
17.8 On-Board Programming Modes........................................................................................ 572
17.9 Programming/Erasing Flash Memory ............................................................................... 579
17.10 Flash Memory Protection.................................................................................................. 585
17.11 Flash Memory Emulation in RAM ................................................................................... 589
17.12 Interrupt Handling when Programming/Erasing Flash Memory....................................... 591
17.13 Flash Memory Writer Mode ............................................................................................. 592
17.14 Flash Memory Programming and Erasing Precautions..................................................... 608
17.15 Notes when Converting the F–ZTAT Application Software to the Mask-ROM Versions 613
Section 18 Clock Pulse Generator
18.1 Overview........................................................................................................................... 615
Rev. 4.00 Feb 15, 2006 page xx of xxiv
17.6.5 Register Configuration......................................................................................... 563
17.7.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 564
17.7.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 566
17.7.3 Erase Block Registers 1 and 2 (EBR1, EBR2)..................................................... 568
17.7.4 System Control Register 2 (SYSCR2) ................................................................. 569
17.7.5 RAM Emulation Register (RAMER)................................................................... 570
17.8.1 Boot Mode ........................................................................................................... 573
17.8.2 User Program Mode............................................................................................. 577
17.9.1 Program Mode ..................................................................................................... 580
17.9.2 Program-Verify Mode.......................................................................................... 581
17.9.3 Erase Mode .......................................................................................................... 583
17.9.4 Erase-Verify Mode .............................................................................................. 583
17.10.1 Hardware Protection ............................................................................................ 585
17.10.2 Software Protection.............................................................................................. 586
17.10.3 Error Protection.................................................................................................... 587
17.11.1 Emulation in RAM............................................................................................... 589
17.11.2 RAM Overlap ...................................................................................................... 590
17.13.1 Writer Mode Setting ............................................................................................ 592
17.13.2 Socket Adapters and Memory Map ..................................................................... 593
17.13.3 Writer Mode Operation........................................................................................ 594
17.13.4 Memory Read Mode ............................................................................................ 596
17.13.5 Auto-Program Mode ............................................................................................ 600
17.13.6 Auto-Erase Mode................................................................................................. 602
17.13.7 Status Read Mode ................................................................................................ 603
17.13.8 Status Polling ....................................................................................................... 605
17.13.9 Writer Mode Transition Time .............................................................................. 606
17.13.10 Notes On Memory Programming..................................................................... 607
18.1.1 Block Diagram ..................................................................................................... 615
18.1.2 Register Configuration......................................................................................... 616
.................................................................................. 615