DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 872

MCU 5V 128K 100-TQFP

DF2345TE20

Manufacturer Part Number
DF2345TE20
Description
MCU 5V 128K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of DF2345TE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
71
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2345TE20
HD64F2345TE20

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Part Number
Manufacturer
Quantity
Price
Part Number:
DF2345TE20V
Manufacturer:
Renesas
Quantity:
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Part Number:
DF2345TE20V
Manufacturer:
Renesas Electronics America
Quantity:
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Appendix B Internal I/O Register
TIOR0L—Timer I/O Control Register 0L
Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register.
Rev. 4.00 Feb 15, 2006 page 846 of 900
REJ09B0291-0400
Bit
Initial value
Read/Write
Notes: 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000, and /1 is used as
TGR0D I/O Control
:
:
:
:
0
1
IOD3
R/W
7
0
0
1
0
1
2. When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register,
the TCNT1 count clock, this setting is invalid and input capture is not generated.
this setting is invalid and input capture/output compare is not generated.
0
1
0
1
0
1
*
IOD2
R/W
0
1
0
1
0
1
0
1
0
1
*
*
6
0
TGR0D
is output
compare
register
TGR0D
is input
capture
register
*
2
IOD1
R/W
5
0
Initial output is
0 output
Output disabled
Initial output is
1 output
Capture input
source is
TIOCD0 pin
Capture input
source is channel
1/count clock
Output disabled
Note: 1. When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register,
IOD0
TGR0C I/O Control
R/W
0
1
4
0
0
1
0
1
this setting is invalid and input capture/output compare is not generated.
IOC3
R/W
0
1
0
1
0
1
*
3
0
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at TCNT1 count-up/
count-down
0
1
0
1
0
1
0
1
0
1
*
*
TGR0C
is output
compare
register
TGR0C
is input
capture
register
*
IOC2
1
R/W
2
0
*
1
H'FFD3
Output disabled
Initial output is
0 output
Output disabled
Initial output is
1 output
Capture input
source is
TIOCC0 pin
Capture input
source is channel
1/count clock
IOC1
R/W
1
0
*: Don’t care
IOC0
R/W
0
0
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at TCNT1 count-up/
count-down
*: Don’t care
TPU0

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