DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 171

• Manufacturer Part Number: DF2345TE20
• Description: MCU 5V 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2345TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2345TE20; HD64F2345TE20

6.3.6
The H8S/2345 Group can output chip select signals (CS0 to CS3) to areas 0 to 3, the signal being
driven low when the corresponding external space area is accessed. In normal mode * , only the
CS0 signal can be output.
Figure 6.3 shows an example of CSn (n = 0 to 3) output timing.
Enabling or disabling of the CSn signal is performed by setting the data direction register (DDR)
for the port corresponding to the particular CSn pin.
In ROM-disabled expansion mode, the CS0 pin is placed in the output state after a power-on reset.
Pins CS1 to CS3 are placed in the input state after a power-on reset, and so the corresponding
DDR should be set to 1 when outputting signals CS1 to CS3.
In ROM-enabled expansion mode, pins CS0 to CS3 are all placed in the input state after a power-
on reset, and so the corresponding DDR should be set to 1 when outputting signals CS0 to CS3.
For details, see section 8, I/O Ports.
Note: * ZTAT, mask ROM, and ROMless versions only.
Chip Select Signals
Address bus
CSn
Figure 6.3 CSn
CSn
CSn
CSn Signal Output Timing (n = 0 to 3)
T
1
Area n external address
Bus cycle
T
2
Rev. 4.00 Feb 15, 2006 page 145 of 900
T
3
Section 6 Bus Controller
REJ09B0291-0400