DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 438

MCU 5V 128K 100-TQFP

DF2345TE20

Manufacturer Part Number
DF2345TE20
Description
MCU 5V 128K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of DF2345TE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
71
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2345TE20
HD64F2345TE20

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2345TE20V
Manufacturer:
Renesas
Quantity:
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Part Number:
DF2345TE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 12 Serial Communication Interface (SCI)
Note: * Descriptions in this section refer to LSB-first transfer.
Rev. 4.00 Feb 15, 2006 page 412 of 900
REJ09B0291-0400
Full-duplex communication capability
On-chip baud rate generator allows any bit rate to be selected
Choice of serial clock source: internal clock from baud rate generator or external clock from
SCK pin
Four interrupt sources
Choice of LSB-first or MSB-first transfer
Module stop mode can be set
The transmitter and receiver are mutually independent, enabling transmission and reception
to be executed simultaneously
Double-buffering is used in both the transmitter and the receiver, enabling continuous
transmission and continuous reception of serial data
Four interrupt sources — transmit-data-empty, transmit-end, receive-data-full, and receive
error — that can issue requests independently
The transmit-data-empty interrupt and receive data full interrupts can activate the data
transfer controller (DTC) to execute data transfer
Can be selected regardless of the communication mode * (except in the case of
asynchronous mode bit data)
As the initial setting, SCI operation is halted. Register access is enabled by exiting module
stop mode.

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