DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 206

• Manufacturer Part Number: DF2345TE20
• Description: MCU 5V 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2345TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2345TE20; HD64F2345TE20

Section 7 Data Transfer Controller
7.2.8
DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by
software, and sets a vector number for the software activation interrupt.
DTVECR is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—DTC Software Activation Enable (SWDTE): Enables or disables DTC activation by
software.
When clearing the SWDTE bit to 0 by software, write 0 to SWDTE after reading SWDTE set to 1.
Bit 7
SWDTE
0
1
Bits 6 to 0—DTC Software Activation Vectors 6 to 0 (DTVEC6 to DTVEC0): These bits
specify a vector number for DTC software activation.
The vector address is expressed as H'0400 + ((vector number) << 1). <<1 indicates a one-bit left-
shift. For example, when DTVEC6 to DTVEC0 = H'10, the vector address is H'0420.
Rev. 4.00 Feb 15, 2006 page 180 of 900
REJ09B0291-0400
Note: *
Bit
Initial value
R/W
DTC Vector Register (DTVECR)
A value of 1 can always be written to the SWDTE bit, but 0 can only be written after 1
is read.
Description
DTC software activation is disabled
[Clearing condition]
When the DISEL bit is 0 and the specified number of transfers have not ended
DTC software activation is enabled
[Holding conditions]
:
:
:
When the DISEL bit is 1 and data transfer has ended
When the specified number of transfers have ended
During data transfer due to software activation
SWDTE
R/(W) *
7
0
DTVEC6
R/W
6
0
DTVEC5
R/W
5
0
DTVEC4
R/W
4
0
DTVEC3
R/W
3
0
DTVEC2
R/W
2
0
DTVEC1
R/W
1
0
(Initial value)
DTVEC0
R/W
0
0