DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 362

MCU 5V 128K 100-TQFP

DF2345TE20

Manufacturer Part Number
DF2345TE20
Description
MCU 5V 128K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of DF2345TE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
71
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2345TE20
HD64F2345TE20

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
DF2345TE20V
Manufacturer:
Renesas
Quantity:
222
Part Number:
DF2345TE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 9 16-Bit Timer Pulse Unit (TPU)
9.4.5
In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit
counter.
This function works by counting the channel 1 (channel 4) counter clock upon overflow/underflow
of TCNT2 (TCNT5) as set in bits TPSC2 to TPSC0 in TCR.
Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.
Table 9.6 shows the register combinations used in cascaded operation.
Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid
Table 9.6
Combination
Channels 1 and 2
Channels 4 and 5
Example of Cascaded Operation Setting Procedure: Figure 9.21 shows an example of the
setting procedure for cascaded operation.
Rev. 4.00 Feb 15, 2006 page 336 of 900
REJ09B0291-0400
and the counter operates independently in phase counting mode.
<Cascaded operation>
Cascaded operation
Cascaded Operation
Set cascading
Cascaded Combinations
Start count
Figure 9.21 Cascaded Operation Setting Procedure
Upper 16 Bits
TCNT1
TCNT4
[1]
[2]
[1] Set bits TPSC2 to TPSC0 in the channel 1
[2] Set the CST bit in TSTR for the upper and lower
(channel 4) TCR to B'111 to select TCNT2
(TCNT5) overflow/underflow counting.
channel to 1 to start the count operation.
Lower 16 Bits
TCNT2
TCNT5

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