DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 263

• Manufacturer Part Number: DF2345TE20
• Description: MCU 5V 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2345TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2345TE20; HD64F2345TE20

Port A Data Register (PADR)
PADR is an 8-bit readable/writable register that stores output data for the port A pins (PA
Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified.
PADR is initialized to H'0 (bits 3 to 0) by a power-on reset, and in hardware standby mode. It
retains its prior state after a manual reset, and in software standby mode.
Port A Register (PORTA)
PORTA is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port A pins (PA
Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified.
If a port A read is performed while PADDR bits are set to 1, the PADR values are read. If a port A
read is performed while PADDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTA contents are determined by the pin
states, as PADDR and PADR are initialized. PORTA retains its prior state after a manual reset,
and in software standby mode.
Note: * Modes 1 to 3 are not available on the F-ZTAT version.
Bit
Initial value
R/W
Bit
Initial value
R/W
Note: * Determined by state of pins PA
Modes 2, 3, 6, and 7 are not available on the ROMless version.
:
:
:
:
:
:
Undefined
Undefined
—
—
—
—
7
7
Undefined
Undefined
—
—
—
—
6
6
3
to PA
Undefined
Undefined
—
—
—
—
5
3
0
5
) must always be performed on PADR.
to PA
Undefined
Undefined
0
.
—
—
—
—
4
4
Rev. 4.00 Feb 15, 2006 page 237 of 900
PA3DR
PA3
R/W
—*
R
3
3
0
PA2DR
PA2
R/W
—*
R
2
2
0
Section 8 I/O Ports
PA1DR
REJ09B0291-0400
PA1
R/W
—*
R
1
1
0
PA0DR
3
PA0
R/W
—*
to PA
R
0
0
0
0
).