DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 401
![MCU 5V 128K 100-TQFP](/photos/28/61/286108/100-tqfp_sml.jpg)
DF2345TE20
Manufacturer Part Number
DF2345TE20
Description
MCU 5V 128K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.DF2345TE20V.pdf
(929 pages)
Specifications of DF2345TE20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
71
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2345TE20
HD64F2345TE20
HD64F2345TE20
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2345TE20V
Manufacturer:
Renesas
Quantity:
222
Company:
Part Number:
DF2345TE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 401 of 929
- Download datasheet (5Mb)
The timer output can be freely controlled by these compare match signals and the settings of bits
OS1 and OS0 of TCSR.
TCORA0 and TCORA1 are each initialized to H'FF by a reset and in hardware standby mode.
10.2.3
Bit
Initial value
R/W
TCORB0 and TCORB1 are 8-bit readable/writable registers. TCORB0 and TCORB1 comprise a
single 16-bit register so they can be accessed together by word transfer instruction.
TCORB is continually compared with the value in TCNT. When a match is detected, the
corresponding CMFB flag of TCSR is set. Note, however, that comparison is disabled during the
T2 state of a TCOR write cycle.
The timer output can be freely controlled by these compare match signals and the settings of
output select bits OS3 and OS2 of TCSR.
TCORB0 and TCORB1 are each initialized to H'FF by a reset and in hardware standby mode.
10.2.4
TCR0 and TCR1 are 8-bit readable/writable registers that select the clock source and the time at
which TCNT is cleared, and enable interrupts.
TCR0 and TCR1 are each initialized to H'00 by a reset and in hardware standby mode.
For details of this timing, see section 10.3, Operation.
Bit
Initial value
R/W
Time Constant Registers B0 and B1 (TCORB0, TCORB1)
Time Control Registers 0 and 1 (TCR0, TCR1)
:
:
:
:
:
:
R/W
15
1
CMIEB
R/W
R/W
14
7
0
1
R/W
13
1
CMIEA
R/W
R/W
TCORB0
6
0
12
1
R/W
11
1
OVIE
R/W
R/W
5
0
10
1
R/W
9
1
CCLR1
R/W
4
0
R/W
8
1
R/W
Rev. 4.00 Feb 15, 2006 page 375 of 900
CCLR0
7
1
R/W
3
0
R/W
6
1
R/W
CKS2
5
1
R/W
2
0
R/W
TCORB1
4
1
Section 10 8-Bit Timers
R/W
CKS1
R/W
3
1
REJ09B0291-0400
1
0
R/W
2
1
R/W
CKS0
R/W
1
1
0
0
R/W
0
1
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