DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 599
![MCU 5V 128K 100-TQFP](/photos/28/61/286108/100-tqfp_sml.jpg)
DF2345TE20
Manufacturer Part Number
DF2345TE20
Description
MCU 5V 128K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.DF2345TE20V.pdf
(929 pages)
Specifications of DF2345TE20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
71
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2345TE20
HD64F2345TE20
HD64F2345TE20
Available stocks
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Company:
Part Number:
DF2345TE20V
Manufacturer:
Renesas
Quantity:
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Part Number:
DF2345TE20V
Manufacturer:
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17.8.1
When boot mode is used, the flash memory programming control program must be prepared in the
host beforehand. The channel 1 SCI to be used is set to asynchronous mode.
When a reset-start is executed after the H8S/2345 MCU’s pins have been set to boot mode, the
boot program built into the MCU is started and the programming control program prepared in the
host is serially transmitted to the MCU via the SCI. In the MCU, the programming control
program received via the SCI is written into the programming control program area in on-chip
RAM. After the transfer is completed, control branches to the start address of the programming
control program area and the programming control program execution state is entered (flash
memory programming is performed).
The transferred programming control program must therefore include coding that follows the
programming algorithm given later.
The system configuration in boot mode is shown in figure 17.15, and the boot program mode
execution procedure in figure 17.16.
Boot Mode
Host
Figure 17.15 System Configuration in Boot Mode
Verify data transmission
Write data reception
Rev. 4.00 Feb 15, 2006 page 573 of 900
RxD1
TxD1
SCI1
H8S/2345 chip
Flash memory
On-chip RAM
REJ09B0291-0400
Section 17 ROM
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