DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 120

• Manufacturer Part Number: DF2345TE20
• Description: MCU 5V 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2345TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2345TE20; HD64F2345TE20

Section 4 Exception Handling
4.2.4
If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state ends, make sure that this instruction initializes
the stack pointer (example: MOV.L #xx:32, SP).
4.2.5
After reset release, MSTPCR is initialized to H'3FFF and all modules except the DTC enter
module stop mode. Consequently, on-chip supporting module registers cannot be read or written
to. Register reading and writing is enabled when module stop mode is exited.
Rev. 4.00 Feb 15, 2006 page 94 of 900
REJ09B0291-0400
RES
Address bus
RD
HWR, LWR
D
(1) (3) Reset exception handling vector address ((1) = H'000000, (3) = H'000002)
(2) (4) Start address (contents of reset exception handling vector address)
(5)
(6)
Note: * 3 program wait states are inserted.
15
Interrupts after Reset
State of On-Chip Supporting Modules after Reset Release
to D
Start address ((5) = (2) (4))
First program instruction
0
Figure 4.3 Reset Sequence (Mode 4)
*
(1)
Vector fetch
(2)
High
*
(3)
Internal
processing
(4)
Prefetch of first
program instruction
(5)
*
(6)