DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 303

• Manufacturer Part Number: DF2345TE20
• Description: MCU 5V 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2345TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2345TE20; HD64F2345TE20

9.1
The H8S/2345 Group has an on-chip 16-bit timer pulse unit (TPU) that comprises six 16-bit timer
channels.
9.1.1
Maximum 16-pulse input/output
Selection of 8 counter input clocks for each channel
The following operations can be set for each channel:
Buffer operation settable for channels 0 and 3
Phase counting mode settable independently for each of channels 1, 2, 4, and 5
Cascaded operation
Fast access via internal 16-bit bus
A total of 16 timer general registers (TGRs) are provided (four each for channels 0 and 3,
and two each for channels 1, 2, 4, and 5), each of which can be set independently as an
output compare/input capture register
TGRC and TGRD for channels 0 and 3 can also be used as buffer registers
Waveform output at compare match: Selection of 0, 1, or toggle output
Input capture function: Selection of rising edge, falling edge, or both edge detection
Counter clear operation: Counter clearing possible by compare match or input capture
Synchronous operation: Multiple timer counters (TCNT) can be written to simultaneously
Simultaneous clearing by compare match and input capture possible
Register simultaneous input/output possible by counter synchronous operation
PWM mode: Any PWM output duty can be set
Maximum of 15-phase PWM output possible by combination with synchronous operation
Input capture register double-buffering possible
Automatic rewriting of output compare register possible
Two-phase encoder pulse up/down-count possible
Channel 2 (channel 5) input clock operates as 32-bit counter by setting channel 1 (channel
4) overflow/underflow
Fast access is possible via a 16-bit bus interface
Features
Overview
Section 9 16-Bit Timer Pulse Unit (TPU)
Rev. 4.00 Feb 15, 2006 page 277 of 900
Section 9 16-Bit Timer Pulse Unit (TPU)
REJ09B0291-0400