DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 188

MCU 5V 128K 100-TQFP

DF2345TE20

Manufacturer Part Number
DF2345TE20
Description
MCU 5V 128K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of DF2345TE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
71
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2345TE20
HD64F2345TE20

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2345TE20V
Manufacturer:
Renesas
Quantity:
222
Part Number:
DF2345TE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 6 Bus Controller
6.6
6.6.1
When the H8S/2345 Group accesses external space, it can insert a 1-state idle cycle (T
bus cycles in the following two cases: (1) when read accesses between different areas occur
consecutively, and (2) when a write cycle occurs immediately after a read cycle. By inserting an
idle cycle it is possible, for example, to avoid data collisions between ROM, with a long output
floating time, and high-speed memory, I/O interfaces, and so on.
(1) Consecutive Reads between Different Areas
If consecutive reads between different areas occur while the ICIS1 bit in BCRH is set to 1, an idle
cycle is inserted at the start of the second read cycle. This is enabled in advanced mode.
Figure 6.16 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM,
each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in
cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,
and a data collision is prevented.
Rev. 4.00 Feb 15, 2006 page 162 of 900
REJ09B0291-0400
Address bus
CS (area A)
CS (area B)
Data bus
RD
Idle Cycle
Operation
(a) Idle cycle not inserted
T
1
Bus cycle A
(ICIS1 = 0)
T
Figure 6.16 Example of Idle Cycle Operation (1)
2
T
Long output
floating time
3
Bus cycle B
T
1
T
2
Data
collision
Address bus
CS (area A)
CS (area B)
Data bus
RD
T
1
(b) Idle cycle inserted
Bus cycle A
(Initial value ICIS1 = 1)
T
2
T
3
T
Bus cycle B
I
I
T
) between
1
T
2

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