DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 298

• Manufacturer Part Number: DF2345TE20
• Description: MCU 5V 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2345TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2345TE20; HD64F2345TE20

Section 8 I/O Ports
Port G Data Direction Register (PGDDR)
PGDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port G. PGDDR cannot be read, and bits 7 to 5 are reserved. If PGDDR is read, an
undefined value will be read.
The PGDDR is initialized by a power-on reset and in hardware standby mode, to H'10 (bits 4 to 0)
in modes 1, 4, and 5 * , and to H'00 (bits 4 to 0) in modes 2, 3, 6, and 7 * . It retains its prior state
after a manual reset and in software standby mode. The OPE bit in SBYCR is used to select
whether the bus control output pins retain their output state or become high-impedance when a
transition is made to software standby mode.
Note: * Modes 1 to 3 are not available on the F-ZTAT version.
Rev. 4.00 Feb 15, 2006 page 272 of 900
REJ09B0291-0400
Bit
Modes 1, 4, 5 *
Initial value
R/W
Modes 2, 3, 6, 7 *
Initial value
R/W
Modes 1 and 2 *
Pin PG
to 1, and as an input port when the bit is cleared to 0.
For pins PG
while clearing the bit to 0 makes the pin an input port.
Modes 3 and 7 *
Setting a PGDDR bit to 1 makes the corresponding port G pin an output port, while clearing
the bit to 0 makes the pin an input port.
Modes 4, 5, and 6 *
Pins PG
PGDDR bits are set to 1, and as input ports when the bits are cleared to 0.
4
Modes 2, 3, 6, and 7 are not available on the ROMless version.
4
functions as a bus control output pin (CS0) when the corresponding PGDDR bit is set
to PG
:
:
:
:
:
3
to PG
Undefined
Undefined
1
function as bus control output pins (CS0 to CS3) when the corresponding
—
—
—
7
0
, setting the corresponding PGDDR bit to 1 makes the pin an output port,
Undefined
Undefined
—
—
—
6
Undefined
Undefined
—
—
—
5
PG4DDR
W
W
4
1
0
PG3DDR
W
W
3
0
0
PG2DDR
W
W
2
0
0
PG1DDR
W
W
1
0
0
PG0DDR
W
W
0
0
0