DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 565

MCU 5V 128K 100-TQFP

DF2345TE20

Manufacturer Part Number
DF2345TE20
Description
MCU 5V 128K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of DF2345TE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
71
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2345TE20
HD64F2345TE20

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2345TE20V
Manufacturer:
Renesas
Quantity:
222
Part Number:
DF2345TE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
16.2
16.2.1
The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details of other bits in
SYSCR, see section 3.2.2, System Control Register (SYSCR).
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset state is released. It is not initialized in software standby mode.
16.3
When the RAME bit is set to 1, accesses to addresses H'FFEC00 to H'FFFBFF (in the case of the
H8S/2345 and H8S/2344) or addresses H'FFF400 to H'FFFBFF (in the case of the H8S/2343,
H8S/2341, and H8S/2340) are directed to the on-chip RAM. When the RAME bit is cleared to 0,
the off-chip address space is accessed.
Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written to
and read in byte or word units. Each type of access can be performed in one state.
Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start
at an even address.
16.4
DTC register information can be located in addresses H'FFF800 to H'FFFBFF. When the DTC is
used, the RAME bit must not be cleared to 0.
Bit 0
RAME
0
1
Bit
Initial value
R/W
Register Descriptions
System Control Register (SYSCR)
Operation
Usage Note
Description
On-chip RAM is disabled
On-chip RAM is enabled
:
:
:
R/W
7
0
R/W
6
0
INTM1
R/W
5
0
INTM0
R/W
4
0
Rev. 4.00 Feb 15, 2006 page 539 of 900
NMIEG
R/W
3
0
R/W
2
0
R/W
REJ09B0291-0400
1
0
Section 16 RAM
(Initial value)
RAME
R/W
0
1

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