DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 157

• Manufacturer Part Number: DF2345TE20
• Description: MCU 5V 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2345TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2345TE20; HD64F2345TE20

6.1.3
Table 6.1 summarizes the pins of the bus controller.
Table 6.1
6.1.4
Table 6.2 summarizes the registers of the bus controller.
Table 6.2
Notes: 1. Lower 16 bits of the address.
Name
Address strobe
Read
High write
Low write
Chip select
0 to 3
Wait
Bus request
Bus request
acknowledge
Name
Bus width control register
Access state control register
Wait control register H
Wait control register L
Bus control register H
Bus control register L
2. Determined by the MCU operating mode.
Pin Configuration
Register Configuration
Bus Controller Pins
Bus Controller Registers
Symbol
AS
RD
HWR
LWR
CS0 to
CS3
WAIT
BREQ
BACK
I/O
Output
Output
Output
Output
Output
Input
Input
Output
Abbreviation
ABWCR
ASTCR
WCRH
WCRL
BCRH
BCRL
Function
Strobe signal indicating that address output on address
bus is enabled.
Strobe signal indicating that external space is being read.
Strobe signal indicating that external space is to be
written, and upper half (D
Strobe signal indicating that external space is to be
written, and lower half (D
Strobe signal indicating that areas 0 to 3 are selected.
Wait request signal when accessing external 3-state
access space.
Request signal that releases bus to external device.
Acknowledge signal indicating that bus has been
released.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 4.00 Feb 15, 2006 page 131 of 900
Power-On
Reset
H'FF/H'00 *
H'FF
H'FF
H'FF
H'D0
H'3C
Initial Value
7
15
to D
to D
2
0
) of data bus is enabled.
8
) of data bus is enabled.
Manual
Reset
Retained
Retained
Retained
Retained
Retained
Retained
Section 6 Bus Controller
REJ09B0291-0400
Address *
H'FED0
H'FED1
H'FED2
H'FED3
H'FED4
H'FED5
1