DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 262

• Manufacturer Part Number: DF2345TE20
• Description: MCU 5V 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2345TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2345TE20; HD64F2345TE20

Section 8 I/O Ports
Port A Data Direction Register (PADDR)
PADDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port A. PADDR cannot be read; if it is, an undefined value will be read. Bits 7 to 4 are
reserved.
PADDR is initialized to H'0 (bits 3 to 0) by a power-on reset and in hardware standby mode. It
retains its prior state after a manual reset, and in software standby mode. The OPE bit in SBYCR
is used to select whether the address output pins retain their output state or become high-
impedance when a transition is made to software standby mode.
Note: * Modes 1 to 3 are not available on the F-ZTAT version.
Rev. 4.00 Feb 15, 2006 page 236 of 900
REJ09B0291-0400
Bit
Initial value
R/W
Modes 1, 2, 3, and 7 *
Setting a PADDR bit to 1 makes the corresponding port A pin an output port, while clearing
the bit to 0 makes the pin an input port.
Modes 4 and 5
The corresponding port A pins are address outputs irrespective of the value of bits PA3DDR to
PA0DDR.
Mode 6 *
Setting a PADDR bit to 1 makes the corresponding port A pin an address output while clearing
the bit to 0 makes the pin an input port.
Modes 2, 3, 6, and 7 are not available on the ROMless version.
:
:
:
Undefined
—
—
7
Undefined
—
—
6
Undefined
—
—
5
Undefined
—
—
4
PA3DDR
W
3
0
PA2DDR
W
2
0
PA1DDR
W
1
0
PA0DDR
W
0
0