DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 508

• Manufacturer Part Number: DF2345TE20
• Description: MCU 5V 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2345TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2345TE20; HD64F2345TE20

Section 13 Smart Card Interface
Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This
function is used together with the SDIR bit for communication with an inverse convention card.
The SINV bit does not affect the logic level of the parity bit. For parity-related setting procedures,
see section 13.3.4, Register Settings.
Bit 2
SINV
0
1
Bit 1—Reserved: Read-only bit, always read as 1.
Bit 0—Smart Card Interface Mode Select (SMIF): Enables or disables the Smart Card interface
function.
Bit 0
SMIF
0
1
13.2.2
Bit 4 of SSR has a different function in Smart Card interface mode. Coupled with this, the setting
conditions for bit 2, TEND, are also different.
Bits 7 to 5—Operate in the same way as for the normal SCI. For details, see section 12.2.7, Serial
Status Register (SSR).
Rev. 4.00 Feb 15, 2006 page 482 of 900
REJ09B0291-0400
Note: * Only 0 can be written to bits 7 to 3, to clear these flags.
Bit
Initial value
R/W
Serial Status Register (SSR)
Description
TDR contents are transmitted as they are
Receive data is stored as it is in RDR
TDR contents are inverted before being transmitted
Receive data is stored in inverted form in RDR
Description
Smart Card interface function is disabled
Smart Card interface function is enabled
:
:
:
R/(W)*
TDRE
7
1
R/(W)*
RDRF
6
0
R/(W)*
ORER
5
0
R/(W)*
ERS
4
0
R/(W)*
PER
3
0
TEND
R
2
1
MPB
R
1
0
(Initial value)
(Initial value)
MPBT
R/W
0
0