DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 190

• Manufacturer Part Number: DF2345TE20
• Description: MCU 5V 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2345TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2345TE20; HD64F2345TE20

Section 6 Bus Controller
(3) Relationship between Chip Select (CS
Depending on the system’s load conditions, the RD signal may lag behind the CS signal. An
example is shown in figure 6.18.
In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap
between the bus cycle A RD signal and the bus cycle B CS signal.
Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS
signals.
In the initial state after reset release, idle cycle insertion (b) is set.
Rev. 4.00 Feb 15, 2006 page 164 of 900
REJ09B0291-0400
Address bus
CS (area A)
CS (area B)
RD
Possibility of overlap between
CS (area B) and RD
Figure 6.18 Relationship between Chip Select (CS
(a) Idle cycle not inserted
T
1
Bus cycle A
(ICIS1 = 0)
T
2
T
3
Bus cycle B
T
1
T
2
CS
CS) Signal and Read (RD
CS
Address bus
CS (area A)
CS (area B)
RD
T
RD
RD) Signal
CS) and Read (RD
CS
CS
RD
1
Bus cycle A
(b) Idle cycle inserted
T
(Initial value ICIS1 = 1)
2
T
3
T
RD)
RD
RD
I
Bus cycle B
T
1
T
2