DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 582

MCU 5V 128K 100-TQFP

DF2345TE20

Manufacturer Part Number
DF2345TE20
Description
MCU 5V 128K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of DF2345TE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
71
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2345TE20
HD64F2345TE20

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2345TE20V
Manufacturer:
Renesas
Quantity:
222
Part Number:
DF2345TE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 17 ROM
17.6.2
Rev. 4.00 Feb 15, 2006 page 556 of 900
REJ09B0291-0400
Protect modes
There are three protect modes, hardware, software, and error protect, which allow protected
status to be designated for flash memory program/erase/verify operations.
Writer mode
Flash memory can be programmed/erased in writer mode, using a PROM programmer, as well
as in on-board programming mode.
Legend:
SYSCR2: System control register 2
FLMCR1: Flash memory control register 1
FLMCR2: Flash memory control register 2
EBR1:
EBR2:
RAMER:
Notes: 1. Functions as FWE pin on F-ZTAT version. Functions as WDTOVF pin on ZTAT,
Block Diagram
2. The flash memory control registers (SYSCR2, FLMCR1, FLMCR2, EBR1, EBR2,
Erase block register 1
Erase block register 2
RAM emulation register
mask ROM, and ROMless versions.
RAMER) are enabled on the F-ZTAT version only. They do not exist on the ZTAT,
mask ROM, and ROMless versions, so an undefined value will be returned if they
are read, and it is not possible to write to these registers.
SYSCR2 *
FLMCR1 *
FLMCR2 *
RAMER *
EBR1 *
EBR2 *
Figure 17.7 Block Diagram of Flash Memory
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
2
2
2
2
2
2
addresses
Bus interface/controller
H'01FFFC H'01FFFD
H'01FFFE H'01FFFF
H'000000 H'000001
H'000002 H'000003
Even
Flash memory
(128 kbytes)
addresses
Odd
Operating
mode
FWE pin *
Mode pins
(MD
2
to MD
1
0
)

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