MC912DG128A Motorola, MC912DG128A Datasheet - Page 116

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

Exception Priority
Maskable interrupts
Resets and Interrupts
MC68HC912DT128A Rev 2.0
116
A hardware priority hierarchy determines which reset or interrupt is
serviced first when simultaneous requests are made. Six sources are not
maskable. The remaining sources are maskable, and any one of them
can be given priority over other maskable interrupts.
The priorities of the non-maskable sources are:
Maskable interrupt sources include on-chip peripheral systems and
external interrupt service requests. Interrupts from these sources are
recognized when the global interrupt mask bit (I) in the CCR is cleared. The
default state of the I bit out of reset is one, but it can be written at any time.
Interrupt sources are prioritized by default but any one maskable interrupt
source may be assigned the highest priority by means of the HPRIO
register. The relative priorities of the other sources remain the same.
An interrupt that is assigned highest priority is still subject to global
masking by the I bit in the CCR, or by any associated local bits. Interrupt
vectors are not affected by priority assignment. HPRIO can only be
written while the I bit is set (interrupts inhibited).
sources and vectors in default order of priority. Before masking an
interrupt by clearing the corresponding local enable bit, it is required to
set the I-bit to avoid an SWI.
1. POR or RESET pin
2. Clock monitor reset
3. COP watchdog reset
4. Unimplemented instruction trap
5. Software interrupt instruction (SWI)
6. XIRQ signal (if X bit in CCR = 0)
Resets and Interrupts
Table 21
lists interrupt
MOTOROLA
2--reset