MC912DG128A Motorola, MC912DG128A Datasheet - Page 201

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

TCTL2 — Timer Control Register 2
TQCR — Reserved
TCTL1 — Timer Control Register 1
15-ect
MOTOROLA
RESET:
RESET:
RESET:
OM3
OM7
Bit 7
Bit 7
Bit 7
NOTE:
0
0
0
OL3
OL7
6
0
6
0
6
0
Read or write anytime.
OMn — Output Mode
OLn — Output Level
To enable output action by OMn and OLn bits on timer port, the
corresponding bit in OC7M should be cleared.
These eight pairs of control bits are encoded to specify the output
action to be taken as a result of a successful OCn compare. When
either OMn or OLn is one, the pin associated with OCn becomes an
output tied to OCn regardless of the state of the associated DDRT bit.
To operate the 16-bit pulse accumulators A and B (PACA and PACB)
independently of input capture or output compare 7 and 0 respectively
the user must set the corresponding bits IOSn = 1, OMn = 0 and OLn
= 0. OC7M7 or OC7M0 in the OC7M register must also be cleared.
OM2
OM6
5
0
5
0
5
0
OMn
0
0
1
1
Enhanced Capture Timer
Table 31 Compare Result Output Action
OL6
OL2
4
0
4
0
4
0
OLn
0
1
0
1
OM5
OM1
3
0
3
0
3
0
Timer disconnected from output pin logic
Clear OCn output line to zero
Set OCn output line to one
OL5
OL1
Toggle OCn output line
2
0
2
0
2
0
Action
OM4
OM0
MC68HC912DT128A Rev 2.0
1
0
1
0
1
0
Timer Register Descriptions
Enhanced Capture Timer
Bit 0
Bit 0
OL4
Bit 0
OL0
0
0
0
$0089
$0087
$0088
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