MC912DG128A Motorola, MC912DG128A Datasheet - Page 167

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

COPCTL — COP Control Register
33-clock
MOTOROLA
RESET:
RESET:
CME
Bit 7
NOTE:
0/1
0/1
FCME
6
0
0
CME — Clock Monitor Enable
The VDDPLL-dependent reset operation is not implemented on first
pass products.
In this case the state of CME on reset is 0.
FCME — Force Clock Monitor Enable
Read and write anytime.
If FCME is set, this bit has no meaning nor effect.
On reset
Write once in normal modes, anytime in special modes. Read
anytime.
In normal modes, when this bit is set, the clock monitor function
cannot be disabled until a reset occurs.
See
0 = Clock monitor is disabled. Slow clocks and stop instruction may
1 = Slow or stopped clocks (including the stop instruction) will
0 = Clock monitor follows the state of the CME bit.
1 = Slow or stopped clocks will cause a clock reset sequence or
FCMCOP
Limp-Home and Fast STOP Recovery
5
0
0
be used.
cause a clock reset sequence or limp-home mode. See
Limp-Home and Fast STOP Recovery
CME is 1 if VDDPLL is high
CME is 0 if VDDPLL is low.
limp-home mode.
WCOP
Clock Functions
4
0
0
DISR
3
0
1
CR2
2
1
1
CR1
modes.
MC68HC912DT128A Rev 2.0
1
1
1
modes.
Clock Function Registers
Bit 0
CR0
1
1
Clock Functions
Special
Normal
$0016
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