MC912DG128A Motorola, MC912DG128A Datasheet - Page 305

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

msCAN12 Identifier Acceptance Control Register (CIDAC)
37-mscan12
MOTOROLA
CIDAC
$0108
RESET
W
R
NOTE:
NOTE:
Bit 7
0
0
The software must not clear one or more of the TXE flags in CTFGL and
simultaneously set the respective ABTRQ bit(s).
TXEIE2 – TXEIE0 — Transmitter Empty Interrupt Enable
The CTCR register is held in the reset state if the SFTRES bit in CMCR0
is set.
IDAM1 – IDAM0 — Identifier Acceptance Mode
IDHIT2 – IDHIT0 — Identifier Acceptance Hit Indicator
The CPU sets these flags to define the identifier acceptance filter
organization (see
the different settings. In Filter Closed mode no messages will be
accepted such that the foreground buffer will never be reloaded.
The msCAN12 sets these flags to indicate an identifier acceptance hit
(see
settings.
6
0
0
0 = No interrupt will be generated from this event.
1 = A transmitter empty (transmit buffer available for transmission)
Identifier Acceptance
event will result in a transmitter empty interrupt.
Table 45 Identifier Acceptance Mode Settings
IDAM1
IDAM1
5
0
0
0
1
1
MSCAN Controller
Identifier Acceptance
IDAM0
IDAM0
4
0
0
1
0
1
Filter).
Four 16 bit Acceptance Filters
Identifier Acceptance Mode
Two 32 bit Acceptance Filters
Eight 8 bit Acceptance Filters
3
0
0
Table 44
Programmer’s Model of Control Registers
Filter Closed
Filter).
IDHIT2
2
0
summarizes the different
MC68HC912DT128A Rev 2.0
Table 44
IDHIT1
1
0
MSCAN Controller
summarizes
IDHIT0
Bit 0
0
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