MC912DG128A Motorola, MC912DG128A Datasheet - Page 182

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

Pulse-Width Modulator
MC68HC912DT128A Rev 2.0
182
PWDTYx — PWM Channel Duty Registers
PWDTY0
PWDTY1
PWDTY2
PWDTY3
RESET:
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
1
and then write the counter forcing a new period to start with the new
period value.
Period = Channel-Clock-Period
Period = Channel-Clock-Period
Read and write anytime.
Left-Aligned-Output Mode (CENTR = 0):
Duty cycle = [(PWDTYx+1) (PWPERx+1)] 100%
Duty cycle = [(PWPERx PWDTYx) (PWPERx+1)] 100%
Center-Aligned-Output Mode (CENTR = 1):
Duty cycle = [(PWPERx PWDTYx) PWPERx]
Duty cycle = [PWDTYx PWPERx]
6
6
6
6
6
1
The value in each duty register determines the duty of the associated
PWM channel. When the duty value is equal to the counter value, the
output changes state. If the register is written while the channel is
enabled, the new value is held in a buffer until the counter rolls over
or the channel is disabled. Reading this register returns the most
recent value written.
If the duty register is greater than or equal to the value in the period
register, there will be no duty change in state. If the duty register is set
to $FF the output will always be in the state which would normally be
the state opposite the PPOLx value.
5
5
5
5
5
1
Pulse-Width Modulator
4
4
4
4
4
1
3
3
3
3
3
1
(PWPER
(2
100%
2
2
2
2
2
1
PWPER)
1
1
1
1
1
1
1)
100%
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
1
(CENTR = 0)
(CENTR = 1)
(PPOLx = 0)
(PPOLx = 1)
(PPOLx = 1)
(PPOLx = 0)
MOTOROLA
$0050
$0051
$0052
$0053
12-pwm