MC912DG128A Motorola, MC912DG128A Datasheet - Page 296

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

msCAN12 Module Control Register (CMCR1)
MSCAN Controller
MC68HC912DT128A Rev 2.0
296
CMCR1
$0101
RESET
W
R
Bit 7
0
0
SFTRES— SOFT_RESET
LOOPB — Loop Back Self Test Mode
When this bit is set by the CPU, the msCAN12 immediately enters the
SOFT_RESET state. Any ongoing transmission or reception is
aborted and synchronization to the bus is lost.
The following registers will go into and stay in the same state as out
of hard reset: CMCR0, CRFLG, CRIER, CTFLG, CTCR.
The registers CMCR1, CBTR0, CBTR1, CIDAC, CIDAR0–3,
CIDMR0–3 can only be written by the CPU when the msCAN12 is in
SOFT_RESET state. The values of the error counters are not affected
by SOFT_RESET.
When this bit is cleared by the CPU, the msCAN12 will try to
synchronize to the CAN bus: If the msCAN12 is not in BUSOFF state
it will be synchronized after 11 recessive bits on the bus; if the
msCAN12 is in BUSOFF state it continues to wait for 128 occurrences
of 11 recessive bits.
Clearing SFTRES and writing to other bits in CMCR0 must be in
separate instructions.
When this bit is set the msCAN12 performs an internal loop back
which can be used for self test operation: the bit stream output of the
transmitter is fed back to the receiver. The RxCAN input pin is ignored
and the TxCAN output goes to the recessive state (1). Note that in this
state the msCAN12 ignores the bit sent during the ACK slot of the
CAN frame Acknowledge field to insure proper reception of its own
message and will treat messages being received while in
transmission as received messages from remote nodes.
6
0
0
0 = Normal operation
1 = msCAN12 in SOFT_RESET state.
0 = Normal operation
1 = Activate loop back self test mode
5
0
0
MSCAN Controller
4
0
0
3
0
0
LOOPB
2
0
WUPM
1
0
MOTOROLA
CLKSRC
28-mscan12
Bit 0
0