MC912DG128A Motorola, MC912DG128A Datasheet - Page 144

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

No Clock at
Power-On Reset
Clock Functions
MC68HC912DT128A Rev 2.0
144
VDD
Power-On Detector
EXTALi
Clock Monitor Fail
Limp-Home
13-stage counter
(Clocked by XCLK)
BCSP
Internal reset
SYSCLK
SYSCLK
(Slow EXTALi)
The voltage level on VDDPLL determines how the MCU responds to an
external clock loss in this case.
With the VDDPLL supply voltage at VDD level, any reset sets the Clock
Monitor Enable bit (CME) and the PLLON bit and clears the NOLHM bit.
Therefore, if the MCU is powered up without an external clock,
limp-home mode is entered provided the MCU is in a normal mode of
operation.
Figure 16 No Clock at Power-On Reset
0 --> 4096
PLLCLK (L.H.)
PLLCLK (Software check of Limp-Home Flag)
Clock Functions
0 --> 4096
EXTALi
(Slow EXTALi)
Reset: BCSP = 0
EXTALi
MOTOROLA
10-clock