MC912DG128A Motorola, MC912DG128A Datasheet - Page 322

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

ATD0STAT1/ATD1STAT1 — ATD Status Register
ATD0STAT0/ATD1STAT0 — ATD Status Register
Analog-To-Digital Converter (ATD)
MC68HC912DT128A Rev 2.0
322
RESET:
RESET:
CCF7
Bit 7
SCF
Bit 7
0
0
CCF6
6
0
0
6
0
The ATD status registers contain the flags indicating the completion of
ATD conversions.
Normally, it is read-only. In special mode, the SCF bit and the CCF bits
may also be written.
SCF — Sequence Complete Flag
CC[2:0] — Conversion Counter for Current Sequence of Four or Eight
Conversions
CCF[7:0] — Conversion Complete Flags
This bit is set at the end of the conversion sequence when in the
single conversion sequence mode (SCAN = 0 in ATDCTL5) and is set
at the end of the first conversion sequence when in the continuous
conversion mode (SCAN = 1 in ATDCTL5). When AFFC = 0, SCF is
cleared when a write is performed to ATDCTL5 to initiate a new
conversion sequence. When AFFC = 1, SCF is cleared after the first
result register is read.
This 3-bit value reflects the contents of the conversion counter pointer
in a four or eight count sequence. This value also reflects which result
register will be written next, indicating which channel is currently
being converted.
Each of these bits are associated with an individual ATD result
register. For each register, this bit is set at the end of conversion for
the associated ATD channel and remains set until that ATD result
register is read. It is cleared at that time if AFFC bit is set, regardless
of whether a status register read has been performed (i.e., a status
CCF5
5
0
0
5
0
Analog-To-Digital Converter (ATD)
CCF4
0
4
0
4
0
CCF3
3
0
0
3
0
CCF2
CC2
2
0
2
0
CCF1
CC1
1
0
1
0
CCF0
Bit 0
CC0
Bit 0
0
0
$0067/$01E7
$0066/$01E6
MOTOROLA
12-atd