MC912DG128A Motorola, MC912DG128A Datasheet - Page 337

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

STATUS— BDM Status Register (1)
STATUS
11-dev
MOTOROLA
RESET:
RESET:
(NOTE 1)
ENBDM
BIT 7
0
0
BDMACT
6
1
0
The content of the INSTRUCTION register is determined by the type of
background command being executed.The STATUS register indicates
BDM operating conditions.The SHIFT register contains data being
received or transmitted via the serial interface. The ADDRESS register
is temporary storage for BDM commands.The CCRSAV register
preserves the content of the CPU12 CCR while BDM is active.
The only registers of interest to users are the STATUS register and the
CCRSAV register.The other BDM registers are only used by the BDM
firmware to execute commands.The registers are accessed by means of
the hardware READ_BD and WRITE_BD commands, but should not be
written during BDM operation (except the CCRSAV register which could
be written to modify the CCR value).
The STATUS register is read and written by the BDM hardware as a
result of serial data shifted in on the BKGD pin.
Read: all modes.
Write: Bits 3 through 5, and bit 7 are writable in all modes. Bit 6,
BDMACT, can only be written if bit 7 H/F in the INSTRUCTION register
is a zero. Bit 2, CLKSW, can only be written if bit 7 H/F in the
INSTRUCTION register is a one. A user would never write ones to bits
3 through 5 because these bits are only used by BDM firmware.
ENTAG
5
0
0
$FF02 - $FF03
$FF04 - $FF05
SDV
Development Support
4
0
0
Address
$FF06
TRACE
Table 58 BDM registers
3
0
0
CLKSW
2
0
0
BDM CCR Holding Register
BDM Address Register
BDM Shift Register
1
0
0
-
Register
MC68HC912DT128A Rev 2.0
Background Debug Mode
BIT 0
Development Support
0
0
-
All other modes
Special Single
Chip & Periph
$FF01
337